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CSI to SPI Peripheral Communication in V850ES Microcontrollers

When CPHA = 1, the master begin driving data at the first edge of SCK. Therefore, the slave unit uses the

first edge of SCK as start of transmission signal. In this clocking mode, the SS_B can remain low (active

chip select state) between transmissions. This clocking method may be preferable for one master and one

slave configuration.

Figure 4. SPI Operation

SPI Control Logic

Transmit/Receive Control, Mode Control, Interrupt Control

Transmit CPU Interrupt Receive Error CPU Interrupt

Internal Data Bus

Transmit Data Register

Shift Register

Receive Data Register

Clock Divider

Clock

Select

Clock Logic

Clock Control Logic

Clock

Input/Output

Control

Logic

SCK

SS_B

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Directed Electronics 3200HS Informazioni Techniche Pagina 12